6024e5c395
clang 20.0.0 (based on r547379) from build 12806354. Bug: http://b/379133546 Test: N/A Change-Id: I2eb8938af55d809de674be63cb30cf27e801862b Upstream-Commit: ad834e67b1105d15ef907f6255d4c96e8e733f57
956 lines
27 KiB
C++
956 lines
27 KiB
C++
//===- llvm/CodeGen/GlobalISel/GenericMachineInstrs.h -----------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// Declares convenience wrapper classes for interpreting MachineInstr instances
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/// as specific generic operations.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_GLOBALISEL_GENERICMACHINEINSTRS_H
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#define LLVM_CODEGEN_GLOBALISEL_GENERICMACHINEINSTRS_H
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#include "llvm/ADT/APInt.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/TargetOpcodes.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/Support/Casting.h"
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namespace llvm {
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/// A base class for all GenericMachineInstrs.
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class GenericMachineInstr : public MachineInstr {
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constexpr static unsigned PoisonFlags = NoUWrap | NoSWrap | NoUSWrap |
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IsExact | Disjoint | NonNeg |
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FmNoNans | FmNoInfs;
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public:
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GenericMachineInstr() = delete;
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/// Access the Idx'th operand as a register and return it.
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/// This assumes that the Idx'th operand is a Register type.
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Register getReg(unsigned Idx) const { return getOperand(Idx).getReg(); }
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static bool classof(const MachineInstr *MI) {
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return isPreISelGenericOpcode(MI->getOpcode());
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}
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bool hasPoisonGeneratingFlags() const { return getFlags() & PoisonFlags; }
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void dropPoisonGeneratingFlags() {
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clearFlags(PoisonFlags);
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assert(!hasPoisonGeneratingFlags());
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}
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};
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/// Provides common memory operand functionality.
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class GMemOperation : public GenericMachineInstr {
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public:
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/// Get the MachineMemOperand on this instruction.
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MachineMemOperand &getMMO() const { return **memoperands_begin(); }
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/// Returns true if the attached MachineMemOperand has the atomic flag set.
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bool isAtomic() const { return getMMO().isAtomic(); }
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/// Returns true if the attached MachineMemOpeand as the volatile flag set.
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bool isVolatile() const { return getMMO().isVolatile(); }
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/// Returns true if the memory operation is neither atomic or volatile.
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bool isSimple() const { return !isAtomic() && !isVolatile(); }
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/// Returns true if this memory operation doesn't have any ordering
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/// constraints other than normal aliasing. Volatile and (ordered) atomic
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/// memory operations can't be reordered.
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bool isUnordered() const { return getMMO().isUnordered(); }
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/// Returns the size in bytes of the memory access.
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LocationSize getMemSize() const { return getMMO().getSize(); }
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/// Returns the size in bits of the memory access.
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LocationSize getMemSizeInBits() const { return getMMO().getSizeInBits(); }
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static bool classof(const MachineInstr *MI) {
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return GenericMachineInstr::classof(MI) && MI->hasOneMemOperand();
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}
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};
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/// Represents any type of generic load or store.
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/// G_LOAD, G_STORE, G_ZEXTLOAD, G_SEXTLOAD.
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class GLoadStore : public GMemOperation {
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public:
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/// Get the source register of the pointer value.
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Register getPointerReg() const { return getOperand(1).getReg(); }
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static bool classof(const MachineInstr *MI) {
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switch (MI->getOpcode()) {
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case TargetOpcode::G_LOAD:
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case TargetOpcode::G_STORE:
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case TargetOpcode::G_ZEXTLOAD:
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case TargetOpcode::G_SEXTLOAD:
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return true;
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default:
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return false;
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}
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}
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};
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/// Represents indexed loads. These are different enough from regular loads
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/// that they get their own class. Including them in GAnyLoad would probably
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/// make a footgun for someone.
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class GIndexedLoad : public GMemOperation {
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public:
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/// Get the definition register of the loaded value.
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Register getDstReg() const { return getOperand(0).getReg(); }
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/// Get the def register of the writeback value.
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Register getWritebackReg() const { return getOperand(1).getReg(); }
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/// Get the base register of the pointer value.
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Register getBaseReg() const { return getOperand(2).getReg(); }
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/// Get the offset register of the pointer value.
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Register getOffsetReg() const { return getOperand(3).getReg(); }
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bool isPre() const { return getOperand(4).getImm() == 1; }
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bool isPost() const { return !isPre(); }
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static bool classof(const MachineInstr *MI) {
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return MI->getOpcode() == TargetOpcode::G_INDEXED_LOAD;
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}
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};
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/// Represents a G_INDEX_ZEXTLOAD/G_INDEXED_SEXTLOAD.
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class GIndexedExtLoad : public GIndexedLoad {
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public:
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static bool classof(const MachineInstr *MI) {
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return MI->getOpcode() == TargetOpcode::G_INDEXED_SEXTLOAD ||
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MI->getOpcode() == TargetOpcode::G_INDEXED_ZEXTLOAD;
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}
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};
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/// Represents either G_INDEXED_LOAD, G_INDEXED_ZEXTLOAD or G_INDEXED_SEXTLOAD.
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class GIndexedAnyExtLoad : public GIndexedLoad {
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public:
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static bool classof(const MachineInstr *MI) {
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switch (MI->getOpcode()) {
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case TargetOpcode::G_INDEXED_LOAD:
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case TargetOpcode::G_INDEXED_ZEXTLOAD:
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case TargetOpcode::G_INDEXED_SEXTLOAD:
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return true;
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default:
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return false;
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}
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}
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};
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/// Represents a G_ZEXTLOAD.
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class GIndexedZExtLoad : GIndexedExtLoad {
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public:
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static bool classof(const MachineInstr *MI) {
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return MI->getOpcode() == TargetOpcode::G_INDEXED_ZEXTLOAD;
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}
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};
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/// Represents a G_SEXTLOAD.
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class GIndexedSExtLoad : GIndexedExtLoad {
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public:
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static bool classof(const MachineInstr *MI) {
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return MI->getOpcode() == TargetOpcode::G_INDEXED_SEXTLOAD;
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}
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};
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/// Represents indexed stores.
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class GIndexedStore : public GMemOperation {
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public:
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/// Get the def register of the writeback value.
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Register getWritebackReg() const { return getOperand(0).getReg(); }
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/// Get the stored value register.
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Register getValueReg() const { return getOperand(1).getReg(); }
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/// Get the base register of the pointer value.
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Register getBaseReg() const { return getOperand(2).getReg(); }
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/// Get the offset register of the pointer value.
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Register getOffsetReg() const { return getOperand(3).getReg(); }
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bool isPre() const { return getOperand(4).getImm() == 1; }
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bool isPost() const { return !isPre(); }
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static bool classof(const MachineInstr *MI) {
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return MI->getOpcode() == TargetOpcode::G_INDEXED_STORE;
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}
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};
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/// Represents any generic load, including sign/zero extending variants.
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class GAnyLoad : public GLoadStore {
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public:
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/// Get the definition register of the loaded value.
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Register getDstReg() const { return getOperand(0).getReg(); }
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/// Returns the Ranges that describes the dereference.
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const MDNode *getRanges() const {
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return getMMO().getRanges();
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}
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static bool classof(const MachineInstr *MI) {
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switch (MI->getOpcode()) {
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case TargetOpcode::G_LOAD:
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case TargetOpcode::G_ZEXTLOAD:
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case TargetOpcode::G_SEXTLOAD:
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return true;
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default:
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return false;
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}
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}
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};
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/// Represents a G_LOAD.
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class GLoad : public GAnyLoad {
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public:
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static bool classof(const MachineInstr *MI) {
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return MI->getOpcode() == TargetOpcode::G_LOAD;
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}
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};
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/// Represents either a G_SEXTLOAD or G_ZEXTLOAD.
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class GExtLoad : public GAnyLoad {
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public:
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static bool classof(const MachineInstr *MI) {
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return MI->getOpcode() == TargetOpcode::G_SEXTLOAD ||
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MI->getOpcode() == TargetOpcode::G_ZEXTLOAD;
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}
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};
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/// Represents a G_SEXTLOAD.
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class GSExtLoad : public GExtLoad {
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public:
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static bool classof(const MachineInstr *MI) {
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return MI->getOpcode() == TargetOpcode::G_SEXTLOAD;
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}
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};
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/// Represents a G_ZEXTLOAD.
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class GZExtLoad : public GExtLoad {
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public:
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static bool classof(const MachineInstr *MI) {
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return MI->getOpcode() == TargetOpcode::G_ZEXTLOAD;
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}
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};
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/// Represents a G_STORE.
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class GStore : public GLoadStore {
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public:
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/// Get the stored value register.
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Register getValueReg() const { return getOperand(0).getReg(); }
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static bool classof(const MachineInstr *MI) {
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return MI->getOpcode() == TargetOpcode::G_STORE;
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}
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};
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/// Represents a G_UNMERGE_VALUES.
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class GUnmerge : public GenericMachineInstr {
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public:
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/// Returns the number of def registers.
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unsigned getNumDefs() const { return getNumOperands() - 1; }
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/// Get the unmerge source register.
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Register getSourceReg() const { return getOperand(getNumDefs()).getReg(); }
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static bool classof(const MachineInstr *MI) {
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return MI->getOpcode() == TargetOpcode::G_UNMERGE_VALUES;
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}
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};
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/// Represents G_BUILD_VECTOR, G_CONCAT_VECTORS or G_MERGE_VALUES.
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/// All these have the common property of generating a single value from
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/// multiple sources.
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class GMergeLikeInstr : public GenericMachineInstr {
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public:
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/// Returns the number of source registers.
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unsigned getNumSources() const { return getNumOperands() - 1; }
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/// Returns the I'th source register.
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Register getSourceReg(unsigned I) const { return getReg(I + 1); }
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static bool classof(const MachineInstr *MI) {
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switch (MI->getOpcode()) {
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case TargetOpcode::G_MERGE_VALUES:
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case TargetOpcode::G_CONCAT_VECTORS:
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case TargetOpcode::G_BUILD_VECTOR:
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return true;
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default:
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return false;
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}
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}
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};
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/// Represents a G_MERGE_VALUES.
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class GMerge : public GMergeLikeInstr {
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public:
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static bool classof(const MachineInstr *MI) {
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return MI->getOpcode() == TargetOpcode::G_MERGE_VALUES;
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}
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};
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/// Represents a G_CONCAT_VECTORS.
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class GConcatVectors : public GMergeLikeInstr {
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public:
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static bool classof(const MachineInstr *MI) {
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return MI->getOpcode() == TargetOpcode::G_CONCAT_VECTORS;
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}
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};
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/// Represents a G_BUILD_VECTOR.
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class GBuildVector : public GMergeLikeInstr {
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public:
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static bool classof(const MachineInstr *MI) {
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return MI->getOpcode() == TargetOpcode::G_BUILD_VECTOR;
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}
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};
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/// Represents a G_BUILD_VECTOR_TRUNC.
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class GBuildVectorTrunc : public GMergeLikeInstr {
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public:
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static bool classof(const MachineInstr *MI) {
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return MI->getOpcode() == TargetOpcode::G_BUILD_VECTOR_TRUNC;
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}
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};
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/// Represents a G_SHUFFLE_VECTOR.
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class GShuffleVector : public GenericMachineInstr {
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public:
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Register getSrc1Reg() const { return getOperand(1).getReg(); }
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Register getSrc2Reg() const { return getOperand(2).getReg(); }
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ArrayRef<int> getMask() const { return getOperand(3).getShuffleMask(); }
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static bool classof(const MachineInstr *MI) {
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return MI->getOpcode() == TargetOpcode::G_SHUFFLE_VECTOR;
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}
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};
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/// Represents a G_PTR_ADD.
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class GPtrAdd : public GenericMachineInstr {
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public:
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Register getBaseReg() const { return getReg(1); }
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Register getOffsetReg() const { return getReg(2); }
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static bool classof(const MachineInstr *MI) {
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return MI->getOpcode() == TargetOpcode::G_PTR_ADD;
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}
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};
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/// Represents a G_IMPLICIT_DEF.
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class GImplicitDef : public GenericMachineInstr {
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public:
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static bool classof(const MachineInstr *MI) {
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return MI->getOpcode() == TargetOpcode::G_IMPLICIT_DEF;
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}
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};
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/// Represents a G_SELECT.
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class GSelect : public GenericMachineInstr {
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public:
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Register getCondReg() const { return getReg(1); }
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Register getTrueReg() const { return getReg(2); }
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Register getFalseReg() const { return getReg(3); }
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static bool classof(const MachineInstr *MI) {
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return MI->getOpcode() == TargetOpcode::G_SELECT;
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}
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};
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/// Represent a G_ICMP or G_FCMP.
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class GAnyCmp : public GenericMachineInstr {
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public:
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CmpInst::Predicate getCond() const {
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return static_cast<CmpInst::Predicate>(getOperand(1).getPredicate());
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}
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Register getLHSReg() const { return getReg(2); }
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Register getRHSReg() const { return getReg(3); }
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static bool classof(const MachineInstr *MI) {
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return MI->getOpcode() == TargetOpcode::G_ICMP ||
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MI->getOpcode() == TargetOpcode::G_FCMP;
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}
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};
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/// Represent a G_ICMP.
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class GICmp : public GAnyCmp {
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public:
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static bool classof(const MachineInstr *MI) {
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return MI->getOpcode() == TargetOpcode::G_ICMP;
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}
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};
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/// Represent a G_FCMP.
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class GFCmp : public GAnyCmp {
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public:
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static bool classof(const MachineInstr *MI) {
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return MI->getOpcode() == TargetOpcode::G_FCMP;
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}
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};
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/// Represents overflowing binary operations.
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/// Only carry-out:
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/// G_UADDO, G_SADDO, G_USUBO, G_SSUBO, G_UMULO, G_SMULO
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/// Carry-in and carry-out:
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/// G_UADDE, G_SADDE, G_USUBE, G_SSUBE
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class GBinOpCarryOut : public GenericMachineInstr {
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public:
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Register getDstReg() const { return getReg(0); }
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Register getCarryOutReg() const { return getReg(1); }
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MachineOperand &getLHS() { return getOperand(2); }
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MachineOperand &getRHS() { return getOperand(3); }
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Register getLHSReg() const { return getOperand(2).getReg(); }
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Register getRHSReg() const { return getOperand(3).getReg(); }
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static bool classof(const MachineInstr *MI) {
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switch (MI->getOpcode()) {
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case TargetOpcode::G_UADDO:
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case TargetOpcode::G_SADDO:
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case TargetOpcode::G_USUBO:
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case TargetOpcode::G_SSUBO:
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case TargetOpcode::G_UADDE:
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case TargetOpcode::G_SADDE:
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case TargetOpcode::G_USUBE:
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case TargetOpcode::G_SSUBE:
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case TargetOpcode::G_UMULO:
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case TargetOpcode::G_SMULO:
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return true;
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default:
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return false;
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}
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}
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};
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/// Represents overflowing add/sub operations.
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/// Only carry-out:
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/// G_UADDO, G_SADDO, G_USUBO, G_SSUBO
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/// Carry-in and carry-out:
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/// G_UADDE, G_SADDE, G_USUBE, G_SSUBE
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class GAddSubCarryOut : public GBinOpCarryOut {
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public:
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bool isAdd() const {
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switch (getOpcode()) {
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case TargetOpcode::G_UADDO:
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case TargetOpcode::G_SADDO:
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case TargetOpcode::G_UADDE:
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case TargetOpcode::G_SADDE:
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return true;
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default:
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return false;
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}
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}
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bool isSub() const { return !isAdd(); }
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bool isSigned() const {
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switch (getOpcode()) {
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case TargetOpcode::G_SADDO:
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case TargetOpcode::G_SSUBO:
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case TargetOpcode::G_SADDE:
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case TargetOpcode::G_SSUBE:
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return true;
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default:
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return false;
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}
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}
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bool isUnsigned() const { return !isSigned(); }
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static bool classof(const MachineInstr *MI) {
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switch (MI->getOpcode()) {
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case TargetOpcode::G_UADDO:
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case TargetOpcode::G_SADDO:
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case TargetOpcode::G_USUBO:
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case TargetOpcode::G_SSUBO:
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case TargetOpcode::G_UADDE:
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case TargetOpcode::G_SADDE:
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case TargetOpcode::G_USUBE:
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case TargetOpcode::G_SSUBE:
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return true;
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default:
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return false;
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}
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}
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};
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/// Represents overflowing add operations.
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/// G_UADDO, G_SADDO
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class GAddCarryOut : public GBinOpCarryOut {
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public:
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bool isSigned() const { return getOpcode() == TargetOpcode::G_SADDO; }
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static bool classof(const MachineInstr *MI) {
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switch (MI->getOpcode()) {
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case TargetOpcode::G_UADDO:
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case TargetOpcode::G_SADDO:
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return true;
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default:
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return false;
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}
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}
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};
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/// Represents overflowing add/sub operations that also consume a carry-in.
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/// G_UADDE, G_SADDE, G_USUBE, G_SSUBE
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class GAddSubCarryInOut : public GAddSubCarryOut {
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public:
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Register getCarryInReg() const { return getReg(4); }
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static bool classof(const MachineInstr *MI) {
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switch (MI->getOpcode()) {
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case TargetOpcode::G_UADDE:
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case TargetOpcode::G_SADDE:
|
|
case TargetOpcode::G_USUBE:
|
|
case TargetOpcode::G_SSUBE:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
};
|
|
|
|
/// Represents a call to an intrinsic.
|
|
class GIntrinsic final : public GenericMachineInstr {
|
|
public:
|
|
Intrinsic::ID getIntrinsicID() const {
|
|
return getOperand(getNumExplicitDefs()).getIntrinsicID();
|
|
}
|
|
|
|
bool is(Intrinsic::ID ID) const { return getIntrinsicID() == ID; }
|
|
|
|
bool hasSideEffects() const {
|
|
switch (getOpcode()) {
|
|
case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
|
|
case TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
bool isConvergent() const {
|
|
switch (getOpcode()) {
|
|
case TargetOpcode::G_INTRINSIC_CONVERGENT:
|
|
case TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
static bool classof(const MachineInstr *MI) {
|
|
switch (MI->getOpcode()) {
|
|
case TargetOpcode::G_INTRINSIC:
|
|
case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
|
|
case TargetOpcode::G_INTRINSIC_CONVERGENT:
|
|
case TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
};
|
|
|
|
// Represents a (non-sequential) vector reduction operation.
|
|
class GVecReduce : public GenericMachineInstr {
|
|
public:
|
|
static bool classof(const MachineInstr *MI) {
|
|
switch (MI->getOpcode()) {
|
|
case TargetOpcode::G_VECREDUCE_FADD:
|
|
case TargetOpcode::G_VECREDUCE_FMUL:
|
|
case TargetOpcode::G_VECREDUCE_FMAX:
|
|
case TargetOpcode::G_VECREDUCE_FMIN:
|
|
case TargetOpcode::G_VECREDUCE_FMAXIMUM:
|
|
case TargetOpcode::G_VECREDUCE_FMINIMUM:
|
|
case TargetOpcode::G_VECREDUCE_ADD:
|
|
case TargetOpcode::G_VECREDUCE_MUL:
|
|
case TargetOpcode::G_VECREDUCE_AND:
|
|
case TargetOpcode::G_VECREDUCE_OR:
|
|
case TargetOpcode::G_VECREDUCE_XOR:
|
|
case TargetOpcode::G_VECREDUCE_SMAX:
|
|
case TargetOpcode::G_VECREDUCE_SMIN:
|
|
case TargetOpcode::G_VECREDUCE_UMAX:
|
|
case TargetOpcode::G_VECREDUCE_UMIN:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
/// Get the opcode for the equivalent scalar operation for this reduction.
|
|
/// E.g. for G_VECREDUCE_FADD, this returns G_FADD.
|
|
unsigned getScalarOpcForReduction() {
|
|
unsigned ScalarOpc;
|
|
switch (getOpcode()) {
|
|
case TargetOpcode::G_VECREDUCE_FADD:
|
|
ScalarOpc = TargetOpcode::G_FADD;
|
|
break;
|
|
case TargetOpcode::G_VECREDUCE_FMUL:
|
|
ScalarOpc = TargetOpcode::G_FMUL;
|
|
break;
|
|
case TargetOpcode::G_VECREDUCE_FMAX:
|
|
ScalarOpc = TargetOpcode::G_FMAXNUM;
|
|
break;
|
|
case TargetOpcode::G_VECREDUCE_FMIN:
|
|
ScalarOpc = TargetOpcode::G_FMINNUM;
|
|
break;
|
|
case TargetOpcode::G_VECREDUCE_FMAXIMUM:
|
|
ScalarOpc = TargetOpcode::G_FMAXIMUM;
|
|
break;
|
|
case TargetOpcode::G_VECREDUCE_FMINIMUM:
|
|
ScalarOpc = TargetOpcode::G_FMINIMUM;
|
|
break;
|
|
case TargetOpcode::G_VECREDUCE_ADD:
|
|
ScalarOpc = TargetOpcode::G_ADD;
|
|
break;
|
|
case TargetOpcode::G_VECREDUCE_MUL:
|
|
ScalarOpc = TargetOpcode::G_MUL;
|
|
break;
|
|
case TargetOpcode::G_VECREDUCE_AND:
|
|
ScalarOpc = TargetOpcode::G_AND;
|
|
break;
|
|
case TargetOpcode::G_VECREDUCE_OR:
|
|
ScalarOpc = TargetOpcode::G_OR;
|
|
break;
|
|
case TargetOpcode::G_VECREDUCE_XOR:
|
|
ScalarOpc = TargetOpcode::G_XOR;
|
|
break;
|
|
case TargetOpcode::G_VECREDUCE_SMAX:
|
|
ScalarOpc = TargetOpcode::G_SMAX;
|
|
break;
|
|
case TargetOpcode::G_VECREDUCE_SMIN:
|
|
ScalarOpc = TargetOpcode::G_SMIN;
|
|
break;
|
|
case TargetOpcode::G_VECREDUCE_UMAX:
|
|
ScalarOpc = TargetOpcode::G_UMAX;
|
|
break;
|
|
case TargetOpcode::G_VECREDUCE_UMIN:
|
|
ScalarOpc = TargetOpcode::G_UMIN;
|
|
break;
|
|
default:
|
|
llvm_unreachable("Unhandled reduction");
|
|
}
|
|
return ScalarOpc;
|
|
}
|
|
};
|
|
|
|
/// Represents a G_PHI.
|
|
class GPhi : public GenericMachineInstr {
|
|
public:
|
|
/// Returns the number of incoming values.
|
|
unsigned getNumIncomingValues() const { return (getNumOperands() - 1) / 2; }
|
|
/// Returns the I'th incoming vreg.
|
|
Register getIncomingValue(unsigned I) const {
|
|
return getOperand(I * 2 + 1).getReg();
|
|
}
|
|
/// Returns the I'th incoming basic block.
|
|
MachineBasicBlock *getIncomingBlock(unsigned I) const {
|
|
return getOperand(I * 2 + 2).getMBB();
|
|
}
|
|
|
|
static bool classof(const MachineInstr *MI) {
|
|
return MI->getOpcode() == TargetOpcode::G_PHI;
|
|
}
|
|
};
|
|
|
|
/// Represents a binary operation, i.e, x = y op z.
|
|
class GBinOp : public GenericMachineInstr {
|
|
public:
|
|
Register getLHSReg() const { return getReg(1); }
|
|
Register getRHSReg() const { return getReg(2); }
|
|
|
|
static bool classof(const MachineInstr *MI) {
|
|
switch (MI->getOpcode()) {
|
|
// Integer.
|
|
case TargetOpcode::G_ADD:
|
|
case TargetOpcode::G_SUB:
|
|
case TargetOpcode::G_MUL:
|
|
case TargetOpcode::G_SDIV:
|
|
case TargetOpcode::G_UDIV:
|
|
case TargetOpcode::G_SREM:
|
|
case TargetOpcode::G_UREM:
|
|
case TargetOpcode::G_SMIN:
|
|
case TargetOpcode::G_SMAX:
|
|
case TargetOpcode::G_UMIN:
|
|
case TargetOpcode::G_UMAX:
|
|
// Floating point.
|
|
case TargetOpcode::G_FMINNUM:
|
|
case TargetOpcode::G_FMAXNUM:
|
|
case TargetOpcode::G_FMINNUM_IEEE:
|
|
case TargetOpcode::G_FMAXNUM_IEEE:
|
|
case TargetOpcode::G_FMINIMUM:
|
|
case TargetOpcode::G_FMAXIMUM:
|
|
case TargetOpcode::G_FADD:
|
|
case TargetOpcode::G_FSUB:
|
|
case TargetOpcode::G_FMUL:
|
|
case TargetOpcode::G_FDIV:
|
|
case TargetOpcode::G_FPOW:
|
|
// Logical.
|
|
case TargetOpcode::G_AND:
|
|
case TargetOpcode::G_OR:
|
|
case TargetOpcode::G_XOR:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
};
|
|
};
|
|
|
|
/// Represents an integer binary operation.
|
|
class GIntBinOp : public GBinOp {
|
|
public:
|
|
static bool classof(const MachineInstr *MI) {
|
|
switch (MI->getOpcode()) {
|
|
case TargetOpcode::G_ADD:
|
|
case TargetOpcode::G_SUB:
|
|
case TargetOpcode::G_MUL:
|
|
case TargetOpcode::G_SDIV:
|
|
case TargetOpcode::G_UDIV:
|
|
case TargetOpcode::G_SREM:
|
|
case TargetOpcode::G_UREM:
|
|
case TargetOpcode::G_SMIN:
|
|
case TargetOpcode::G_SMAX:
|
|
case TargetOpcode::G_UMIN:
|
|
case TargetOpcode::G_UMAX:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
};
|
|
};
|
|
|
|
/// Represents a floating point binary operation.
|
|
class GFBinOp : public GBinOp {
|
|
public:
|
|
static bool classof(const MachineInstr *MI) {
|
|
switch (MI->getOpcode()) {
|
|
case TargetOpcode::G_FMINNUM:
|
|
case TargetOpcode::G_FMAXNUM:
|
|
case TargetOpcode::G_FMINNUM_IEEE:
|
|
case TargetOpcode::G_FMAXNUM_IEEE:
|
|
case TargetOpcode::G_FMINIMUM:
|
|
case TargetOpcode::G_FMAXIMUM:
|
|
case TargetOpcode::G_FADD:
|
|
case TargetOpcode::G_FSUB:
|
|
case TargetOpcode::G_FMUL:
|
|
case TargetOpcode::G_FDIV:
|
|
case TargetOpcode::G_FPOW:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
};
|
|
};
|
|
|
|
/// Represents a logical binary operation.
|
|
class GLogicalBinOp : public GBinOp {
|
|
public:
|
|
static bool classof(const MachineInstr *MI) {
|
|
switch (MI->getOpcode()) {
|
|
case TargetOpcode::G_AND:
|
|
case TargetOpcode::G_OR:
|
|
case TargetOpcode::G_XOR:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
};
|
|
};
|
|
|
|
/// Represents an integer addition.
|
|
class GAdd : public GIntBinOp {
|
|
public:
|
|
static bool classof(const MachineInstr *MI) {
|
|
return MI->getOpcode() == TargetOpcode::G_ADD;
|
|
};
|
|
};
|
|
|
|
/// Represents a logical and.
|
|
class GAnd : public GLogicalBinOp {
|
|
public:
|
|
static bool classof(const MachineInstr *MI) {
|
|
return MI->getOpcode() == TargetOpcode::G_AND;
|
|
};
|
|
};
|
|
|
|
/// Represents a logical or.
|
|
class GOr : public GLogicalBinOp {
|
|
public:
|
|
static bool classof(const MachineInstr *MI) {
|
|
return MI->getOpcode() == TargetOpcode::G_OR;
|
|
};
|
|
};
|
|
|
|
/// Represents an extract vector element.
|
|
class GExtractVectorElement : public GenericMachineInstr {
|
|
public:
|
|
Register getVectorReg() const { return getOperand(1).getReg(); }
|
|
Register getIndexReg() const { return getOperand(2).getReg(); }
|
|
|
|
static bool classof(const MachineInstr *MI) {
|
|
return MI->getOpcode() == TargetOpcode::G_EXTRACT_VECTOR_ELT;
|
|
}
|
|
};
|
|
|
|
/// Represents an insert vector element.
|
|
class GInsertVectorElement : public GenericMachineInstr {
|
|
public:
|
|
Register getVectorReg() const { return getOperand(1).getReg(); }
|
|
Register getElementReg() const { return getOperand(2).getReg(); }
|
|
Register getIndexReg() const { return getOperand(3).getReg(); }
|
|
|
|
static bool classof(const MachineInstr *MI) {
|
|
return MI->getOpcode() == TargetOpcode::G_INSERT_VECTOR_ELT;
|
|
}
|
|
};
|
|
|
|
/// Represents a freeze.
|
|
class GFreeze : public GenericMachineInstr {
|
|
public:
|
|
Register getSourceReg() const { return getOperand(1).getReg(); }
|
|
|
|
static bool classof(const MachineInstr *MI) {
|
|
return MI->getOpcode() == TargetOpcode::G_FREEZE;
|
|
}
|
|
};
|
|
|
|
/// Represents a cast operation.
|
|
/// It models the llvm::CastInst concept.
|
|
/// The exception is bitcast.
|
|
class GCastOp : public GenericMachineInstr {
|
|
public:
|
|
Register getSrcReg() const { return getOperand(1).getReg(); }
|
|
|
|
static bool classof(const MachineInstr *MI) {
|
|
switch (MI->getOpcode()) {
|
|
case TargetOpcode::G_ADDRSPACE_CAST:
|
|
case TargetOpcode::G_FPEXT:
|
|
case TargetOpcode::G_FPTOSI:
|
|
case TargetOpcode::G_FPTOUI:
|
|
case TargetOpcode::G_FPTRUNC:
|
|
case TargetOpcode::G_INTTOPTR:
|
|
case TargetOpcode::G_PTRTOINT:
|
|
case TargetOpcode::G_SEXT:
|
|
case TargetOpcode::G_SITOFP:
|
|
case TargetOpcode::G_TRUNC:
|
|
case TargetOpcode::G_UITOFP:
|
|
case TargetOpcode::G_ZEXT:
|
|
case TargetOpcode::G_ANYEXT:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
};
|
|
};
|
|
|
|
/// Represents a sext.
|
|
class GSext : public GCastOp {
|
|
public:
|
|
static bool classof(const MachineInstr *MI) {
|
|
return MI->getOpcode() == TargetOpcode::G_SEXT;
|
|
};
|
|
};
|
|
|
|
/// Represents a zext.
|
|
class GZext : public GCastOp {
|
|
public:
|
|
static bool classof(const MachineInstr *MI) {
|
|
return MI->getOpcode() == TargetOpcode::G_ZEXT;
|
|
};
|
|
};
|
|
|
|
/// Represents a trunc.
|
|
class GTrunc : public GCastOp {
|
|
public:
|
|
static bool classof(const MachineInstr *MI) {
|
|
return MI->getOpcode() == TargetOpcode::G_TRUNC;
|
|
};
|
|
};
|
|
|
|
/// Represents a vscale.
|
|
class GVScale : public GenericMachineInstr {
|
|
public:
|
|
APInt getSrc() const { return getOperand(1).getCImm()->getValue(); }
|
|
|
|
static bool classof(const MachineInstr *MI) {
|
|
return MI->getOpcode() == TargetOpcode::G_VSCALE;
|
|
};
|
|
};
|
|
|
|
/// Represents an integer subtraction.
|
|
class GSub : public GIntBinOp {
|
|
public:
|
|
static bool classof(const MachineInstr *MI) {
|
|
return MI->getOpcode() == TargetOpcode::G_SUB;
|
|
};
|
|
};
|
|
|
|
/// Represents an integer multiplication.
|
|
class GMul : public GIntBinOp {
|
|
public:
|
|
static bool classof(const MachineInstr *MI) {
|
|
return MI->getOpcode() == TargetOpcode::G_MUL;
|
|
};
|
|
};
|
|
|
|
/// Represents a shift left.
|
|
class GShl : public GenericMachineInstr {
|
|
public:
|
|
Register getSrcReg() const { return getOperand(1).getReg(); }
|
|
Register getShiftReg() const { return getOperand(2).getReg(); }
|
|
|
|
static bool classof(const MachineInstr *MI) {
|
|
return MI->getOpcode() == TargetOpcode::G_SHL;
|
|
};
|
|
};
|
|
|
|
/// Represents a threeway compare.
|
|
class GSUCmp : public GenericMachineInstr {
|
|
public:
|
|
Register getLHSReg() const { return getOperand(1).getReg(); }
|
|
Register getRHSReg() const { return getOperand(2).getReg(); }
|
|
|
|
bool isSigned() const { return getOpcode() == TargetOpcode::G_SCMP; }
|
|
|
|
static bool classof(const MachineInstr *MI) {
|
|
switch (MI->getOpcode()) {
|
|
case TargetOpcode::G_SCMP:
|
|
case TargetOpcode::G_UCMP:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
};
|
|
};
|
|
|
|
/// Represents an integer-like extending operation.
|
|
class GExtOp : public GCastOp {
|
|
public:
|
|
static bool classof(const MachineInstr *MI) {
|
|
switch (MI->getOpcode()) {
|
|
case TargetOpcode::G_SEXT:
|
|
case TargetOpcode::G_ZEXT:
|
|
case TargetOpcode::G_ANYEXT:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
};
|
|
};
|
|
|
|
/// Represents an integer-like extending or truncating operation.
|
|
class GExtOrTruncOp : public GCastOp {
|
|
public:
|
|
static bool classof(const MachineInstr *MI) {
|
|
switch (MI->getOpcode()) {
|
|
case TargetOpcode::G_SEXT:
|
|
case TargetOpcode::G_ZEXT:
|
|
case TargetOpcode::G_ANYEXT:
|
|
case TargetOpcode::G_TRUNC:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
};
|
|
};
|
|
|
|
} // namespace llvm
|
|
|
|
#endif // LLVM_CODEGEN_GLOBALISEL_GENERICMACHINEINSTRS_H
|