6024e5c395
clang 20.0.0 (based on r547379) from build 12806354. Bug: http://b/379133546 Test: N/A Change-Id: I2eb8938af55d809de674be63cb30cf27e801862b Upstream-Commit: ad834e67b1105d15ef907f6255d4c96e8e733f57
128 lines
3.7 KiB
C++
128 lines
3.7 KiB
C++
//===-- RISCVTargetParser - Parser for target features ----------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a target parser to recognise hardware features
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// for RISC-V CPUs.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGETPARSER_RISCVTARGETPARSER_H
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#define LLVM_TARGETPARSER_RISCVTARGETPARSER_H
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#include "llvm/ADT/StringRef.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/raw_ostream.h"
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namespace llvm {
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class Triple;
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namespace RISCV {
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namespace RISCVExtensionBitmaskTable {
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struct RISCVExtensionBitmask {
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const char *Name;
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unsigned GroupID;
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unsigned BitPosition;
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};
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} // namespace RISCVExtensionBitmaskTable
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// We use 64 bits as the known part in the scalable vector types.
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static constexpr unsigned RVVBitsPerBlock = 64;
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void getFeaturesForCPU(StringRef CPU,
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SmallVectorImpl<std::string> &EnabledFeatures,
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bool NeedPlus = false);
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bool parseCPU(StringRef CPU, bool IsRV64);
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bool parseTuneCPU(StringRef CPU, bool IsRV64);
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StringRef getMArchFromMcpu(StringRef CPU);
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void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
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void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
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bool hasFastScalarUnalignedAccess(StringRef CPU);
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bool hasFastVectorUnalignedAccess(StringRef CPU);
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} // namespace RISCV
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namespace RISCVII {
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enum VLMUL : uint8_t {
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LMUL_1 = 0,
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LMUL_2,
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LMUL_4,
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LMUL_8,
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LMUL_RESERVED,
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LMUL_F8,
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LMUL_F4,
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LMUL_F2
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};
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enum {
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TAIL_UNDISTURBED_MASK_UNDISTURBED = 0,
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TAIL_AGNOSTIC = 1,
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MASK_AGNOSTIC = 2,
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};
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} // namespace RISCVII
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namespace RISCVVType {
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// Is this a SEW value that can be encoded into the VTYPE format.
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inline static bool isValidSEW(unsigned SEW) {
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return isPowerOf2_32(SEW) && SEW >= 8 && SEW <= 64;
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}
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// Is this a LMUL value that can be encoded into the VTYPE format.
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inline static bool isValidLMUL(unsigned LMUL, bool Fractional) {
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return isPowerOf2_32(LMUL) && LMUL <= 8 && (!Fractional || LMUL != 1);
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}
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unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic,
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bool MaskAgnostic);
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inline static RISCVII::VLMUL getVLMUL(unsigned VType) {
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unsigned VLMUL = VType & 0x7;
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return static_cast<RISCVII::VLMUL>(VLMUL);
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}
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// Decode VLMUL into 1,2,4,8 and fractional indicator.
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std::pair<unsigned, bool> decodeVLMUL(RISCVII::VLMUL VLMUL);
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inline static RISCVII::VLMUL encodeLMUL(unsigned LMUL, bool Fractional) {
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assert(isValidLMUL(LMUL, Fractional) && "Unsupported LMUL");
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unsigned LmulLog2 = Log2_32(LMUL);
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return static_cast<RISCVII::VLMUL>(Fractional ? 8 - LmulLog2 : LmulLog2);
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}
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inline static unsigned decodeVSEW(unsigned VSEW) {
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assert(VSEW < 8 && "Unexpected VSEW value");
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return 1 << (VSEW + 3);
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}
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inline static unsigned encodeSEW(unsigned SEW) {
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assert(isValidSEW(SEW) && "Unexpected SEW value");
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return Log2_32(SEW) - 3;
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}
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inline static unsigned getSEW(unsigned VType) {
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unsigned VSEW = (VType >> 3) & 0x7;
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return decodeVSEW(VSEW);
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}
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inline static bool isTailAgnostic(unsigned VType) { return VType & 0x40; }
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inline static bool isMaskAgnostic(unsigned VType) { return VType & 0x80; }
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void printVType(unsigned VType, raw_ostream &OS);
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unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul);
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std::optional<RISCVII::VLMUL>
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getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL, unsigned EEW);
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} // namespace RISCVVType
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} // namespace llvm
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#endif
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