6024e5c395
clang 20.0.0 (based on r547379) from build 12806354. Bug: http://b/379133546 Test: N/A Change-Id: I2eb8938af55d809de674be63cb30cf27e801862b Upstream-Commit: ad834e67b1105d15ef907f6255d4c96e8e733f57
290 lines
11 KiB
C++
290 lines
11 KiB
C++
//===-- AArch64TargetParser - Parser for AArch64 features -------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a target parser to recognise AArch64 hardware features
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// such as FPU/CPU/ARCH and extension names.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGETPARSER_AARCH64TARGETPARSER_H
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#define LLVM_TARGETPARSER_AARCH64TARGETPARSER_H
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/Bitset.h"
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#include "llvm/ADT/StringMap.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/Support/VersionTuple.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/TargetParser/SubtargetFeature.h"
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#include <array>
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#include <set>
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#include <vector>
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namespace llvm {
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class Triple;
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namespace AArch64 {
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struct ArchInfo;
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struct CpuInfo;
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#include "llvm/TargetParser/AArch64CPUFeatures.inc"
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static_assert(FEAT_MAX < 62,
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"Number of features in CPUFeatures are limited to 62 entries");
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// Each ArchExtKind correponds directly to a possible -target-feature.
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#define EMIT_ARCHEXTKIND_ENUM
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#include "llvm/TargetParser/AArch64TargetParserDef.inc"
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using ExtensionBitset = Bitset<AEK_NUM_EXTENSIONS>;
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// Represents an extension that can be enabled with -march=<arch>+<extension>.
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// Typically these correspond to Arm Architecture extensions, unlike
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// SubtargetFeature which may represent either an actual extension or some
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// internal LLVM property.
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struct ExtensionInfo {
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StringRef UserVisibleName; // Human readable name used in -march, -cpu
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// and target func attribute, e.g. "profile".
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std::optional<StringRef> Alias; // An alias for this extension, if one exists.
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ArchExtKind ID; // Corresponding to the ArchExtKind, this
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// extensions representation in the bitfield.
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StringRef ArchFeatureName; // The feature name defined by the
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// Architecture, e.g. FEAT_AdvSIMD.
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StringRef Description; // The textual description of the extension.
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StringRef PosTargetFeature; // -target-feature/-mattr enable string,
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// e.g. "+spe".
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StringRef NegTargetFeature; // -target-feature/-mattr disable string,
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// e.g. "-spe".
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};
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#define EMIT_EXTENSIONS
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#include "llvm/TargetParser/AArch64TargetParserDef.inc"
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struct FMVInfo {
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StringRef Name; // The target_version/target_clones spelling.
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CPUFeatures Bit; // Index of the bit in the FMV feature bitset.
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StringRef Features; // List of SubtargetFeatures to enable.
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unsigned Priority; // FMV priority.
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FMVInfo(StringRef Name, CPUFeatures Bit, StringRef Features,
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unsigned Priority)
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: Name(Name), Bit(Bit), Features(Features), Priority(Priority){};
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SmallVector<StringRef, 8> getImpliedFeatures() {
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SmallVector<StringRef, 8> Feats;
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Features.split(Feats, ',', -1, false); // discard empty strings
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return Feats;
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}
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};
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const std::vector<FMVInfo> &getFMVInfo();
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// Represents a dependency between two architecture extensions. Later is the
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// feature which was added to the architecture after Earlier, and expands the
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// functionality provided by it. If Later is enabled, then Earlier will also be
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// enabled. If Earlier is disabled, then Later will also be disabled.
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struct ExtensionDependency {
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ArchExtKind Earlier;
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ArchExtKind Later;
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};
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#define EMIT_EXTENSION_DEPENDENCIES
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#include "llvm/TargetParser/AArch64TargetParserDef.inc"
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enum ArchProfile { AProfile = 'A', RProfile = 'R', InvalidProfile = '?' };
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// Information about a specific architecture, e.g. V8.1-A
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struct ArchInfo {
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VersionTuple Version; // Architecture version, major + minor.
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ArchProfile Profile; // Architecuture profile
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StringRef Name; // Name as supplied to -march e.g. "armv8.1-a"
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StringRef ArchFeature; // Name as supplied to -target-feature, e.g. "+v8a"
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AArch64::ExtensionBitset
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DefaultExts; // bitfield of default extensions ArchExtKind
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bool operator==(const ArchInfo &Other) const {
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return this->Name == Other.Name;
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}
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bool operator!=(const ArchInfo &Other) const {
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return this->Name != Other.Name;
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}
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// Defines the following partial order, indicating when an architecture is
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// a superset of another:
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//
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// v9.5a > v9.4a > v9.3a > v9.2a > v9.1a > v9a;
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// v v v v v
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// v8.9a > v8.8a > v8.7a > v8.6a > v8.5a > v8.4a > ... > v8a;
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//
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// v8r has no relation to anything. This is used to determine which
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// features to enable for a given architecture. See
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// AArch64TargetInfo::setFeatureEnabled.
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bool implies(const ArchInfo &Other) const {
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if (this->Profile != Other.Profile)
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return false; // ARMV8R
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if (this->Version.getMajor() == Other.Version.getMajor()) {
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return this->Version > Other.Version;
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}
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if (this->Version.getMajor() == 9 && Other.Version.getMajor() == 8) {
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assert(this->Version.getMinor() && Other.Version.getMinor() &&
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"AArch64::ArchInfo should have a minor version.");
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return this->Version.getMinor().value_or(0) + 5 >=
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Other.Version.getMinor().value_or(0);
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}
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return false;
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}
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// True if this architecture is a superset of Other (including being equal to
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// it).
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bool is_superset(const ArchInfo &Other) const {
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return (*this == Other) || implies(Other);
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}
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// Return ArchFeature without the leading "+".
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StringRef getSubArch() const { return ArchFeature.substr(1); }
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// Search for ArchInfo by SubArch name
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static std::optional<ArchInfo> findBySubArch(StringRef SubArch);
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};
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#define EMIT_ARCHITECTURES
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#include "llvm/TargetParser/AArch64TargetParserDef.inc"
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// Details of a specific CPU.
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struct CpuInfo {
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StringRef Name; // Name, as written for -mcpu.
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const ArchInfo &Arch;
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AArch64::ExtensionBitset
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DefaultExtensions; // Default extensions for this CPU.
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AArch64::ExtensionBitset getImpliedExtensions() const {
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return DefaultExtensions;
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}
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};
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#define EMIT_CPU_INFO
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#include "llvm/TargetParser/AArch64TargetParserDef.inc"
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struct ExtensionSet {
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// Set of extensions which are currently enabled.
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ExtensionBitset Enabled;
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// Set of extensions which have been enabled or disabled at any point. Used
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// to avoid cluttering the cc1 command-line with lots of unneeded features.
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ExtensionBitset Touched;
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// Base architecture version, which we need to know because some feature
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// dependencies change depending on this.
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const ArchInfo *BaseArch;
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ExtensionSet() : Enabled(), Touched(), BaseArch(nullptr) {}
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// Enable the given architecture extension, and any other extensions it
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// depends on. Does not change the base architecture, or follow dependencies
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// between features which are only related by required arcitecture versions.
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void enable(ArchExtKind E);
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// Disable the given architecture extension, and any other extensions which
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// depend on it. Does not change the base architecture, or follow
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// dependencies between features which are only related by required
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// arcitecture versions.
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void disable(ArchExtKind E);
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// Add default extensions for the given CPU. Records the base architecture,
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// to later resolve dependencies which depend on it.
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void addCPUDefaults(const CpuInfo &CPU);
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// Add default extensions for the given architecture version. Records the
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// base architecture, to later resolve dependencies which depend on it.
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void addArchDefaults(const ArchInfo &Arch);
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// Add or remove a feature based on a modifier string. The string must be of
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// the form "<name>" to enable a feature or "no<name>" to disable it. This
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// will also enable or disable any features as required by the dependencies
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// between them.
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bool parseModifier(StringRef Modifier, const bool AllowNoDashForm = false);
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// Constructs a new ExtensionSet by toggling the corresponding bits for every
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// feature in the \p Features list without expanding their dependencies. Used
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// for reconstructing an ExtensionSet from the output of toLLVMFeatures().
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// Features that are not recognized are pushed back to \p NonExtensions.
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void reconstructFromParsedFeatures(const std::vector<std::string> &Features,
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std::vector<std::string> &NonExtensions);
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// Convert the set of enabled extension to an LLVM feature list, appending
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// them to Features.
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template <typename T> void toLLVMFeatureList(std::vector<T> &Features) const {
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if (BaseArch && !BaseArch->ArchFeature.empty())
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Features.emplace_back(T(BaseArch->ArchFeature));
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for (const auto &E : Extensions) {
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if (E.PosTargetFeature.empty() || !Touched.test(E.ID))
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continue;
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if (Enabled.test(E.ID))
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Features.emplace_back(T(E.PosTargetFeature));
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else
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Features.emplace_back(T(E.NegTargetFeature));
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}
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}
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void dump() const;
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};
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// Name alias.
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struct Alias {
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StringRef AltName;
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StringRef Name;
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};
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#define EMIT_CPU_ALIAS
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#include "llvm/TargetParser/AArch64TargetParserDef.inc"
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const ExtensionInfo &getExtensionByID(ArchExtKind(ExtID));
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bool getExtensionFeatures(
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const AArch64::ExtensionBitset &Extensions,
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std::vector<StringRef> &Features);
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StringRef getArchExtFeature(StringRef ArchExt);
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StringRef resolveCPUAlias(StringRef CPU);
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// Information by Name
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const ArchInfo *getArchForCpu(StringRef CPU);
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// Parser
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const ArchInfo *parseArch(StringRef Arch);
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// Return the extension which has the given -target-feature name.
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std::optional<ExtensionInfo> targetFeatureToExtension(StringRef TargetFeature);
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// Parse a name as defined by the Extension class in tablegen.
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std::optional<ExtensionInfo> parseArchExtension(StringRef Extension);
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// Parse a name as defined by the FMVInfo class in tablegen.
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std::optional<FMVInfo> parseFMVExtension(StringRef Extension);
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// Given the name of a CPU or alias, return the correponding CpuInfo.
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std::optional<CpuInfo> parseCpu(StringRef Name);
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// Used by target parser tests
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void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values);
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bool isX18ReservedByDefault(const Triple &TT);
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// For given feature names, return a bitmask corresponding to the entries of
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// AArch64::CPUFeatures. The values in CPUFeatures are not bitmasks
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// themselves, they are sequential (0, 1, 2, 3, ...).
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uint64_t getCpuSupportsMask(ArrayRef<StringRef> FeatureStrs);
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void PrintSupportedExtensions();
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void printEnabledExtensions(const std::set<StringRef> &EnabledFeatureNames);
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} // namespace AArch64
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} // namespace llvm
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#endif
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