6024e5c395
clang 20.0.0 (based on r547379) from build 12806354. Bug: http://b/379133546 Test: N/A Change-Id: I2eb8938af55d809de674be63cb30cf27e801862b Upstream-Commit: ad834e67b1105d15ef907f6255d4c96e8e733f57
94 lines
4.6 KiB
TableGen
94 lines
4.6 KiB
TableGen
//===- IntrinsicsRISCVXCV.td - CORE-V intrinsics -----------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines all of the CORE-V vendor intrinsics for RISC-V.
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//
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//===----------------------------------------------------------------------===//
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class ScalarCoreVBitManipGprGprIntrinsic
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: DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
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[IntrNoMem, IntrSpeculatable]>;
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class ScalarCoreVBitManipGprIntrinsic
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: DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty],
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[IntrNoMem, IntrSpeculatable]>;
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class ScalarCoreVAluGprIntrinsic
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: DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty],
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[IntrNoMem, IntrSpeculatable]>;
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class ScalarCoreVAluGprGprIntrinsic
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: DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
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[IntrNoMem, IntrSpeculatable]>;
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class ScalarCoreVAluGprGprGprIntrinsic
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: DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
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[IntrNoMem, IntrSpeculatable]>;
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class ScalarCoreVMacGprGprGprIntrinsic
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: Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
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[IntrNoMem, IntrWillReturn, IntrSpeculatable]>;
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class ScalarCoreVMacGprGPRImmIntrinsic
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: Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
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[IntrNoMem, IntrWillReturn, IntrSpeculatable, ImmArg<ArgIndex<2>>]>;
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class ScalarCoreVMacGprGprGprImmIntrinsic
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: Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
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[IntrNoMem, IntrWillReturn, IntrSpeculatable, ImmArg<ArgIndex<3>>]>;
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let TargetPrefix = "riscv" in {
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def int_riscv_cv_bitmanip_extract : ScalarCoreVBitManipGprGprIntrinsic;
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def int_riscv_cv_bitmanip_extractu : ScalarCoreVBitManipGprGprIntrinsic;
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def int_riscv_cv_bitmanip_bclr : ScalarCoreVBitManipGprGprIntrinsic;
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def int_riscv_cv_bitmanip_bset : ScalarCoreVBitManipGprGprIntrinsic;
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def int_riscv_cv_bitmanip_insert
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: DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
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[IntrNoMem, IntrSpeculatable]>;
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def int_riscv_cv_bitmanip_clb : ScalarCoreVBitManipGprIntrinsic;
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def int_riscv_cv_bitmanip_bitrev
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: DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
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[IntrNoMem, IntrWillReturn, IntrSpeculatable,
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ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>;
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def int_riscv_cv_alu_clip : ScalarCoreVAluGprGprIntrinsic;
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def int_riscv_cv_alu_clipu : ScalarCoreVAluGprGprIntrinsic;
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def int_riscv_cv_alu_addn : ScalarCoreVAluGprGprGprIntrinsic;
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def int_riscv_cv_alu_addun : ScalarCoreVAluGprGprGprIntrinsic;
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def int_riscv_cv_alu_addrn : ScalarCoreVAluGprGprGprIntrinsic;
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def int_riscv_cv_alu_addurn : ScalarCoreVAluGprGprGprIntrinsic;
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def int_riscv_cv_alu_subn : ScalarCoreVAluGprGprGprIntrinsic;
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def int_riscv_cv_alu_subun : ScalarCoreVAluGprGprGprIntrinsic;
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def int_riscv_cv_alu_subrn : ScalarCoreVAluGprGprGprIntrinsic;
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def int_riscv_cv_alu_suburn : ScalarCoreVAluGprGprGprIntrinsic;
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def int_riscv_cv_mac_mac : ScalarCoreVMacGprGprGprIntrinsic;
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def int_riscv_cv_mac_msu : ScalarCoreVMacGprGprGprIntrinsic;
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def int_riscv_cv_mac_muluN : ScalarCoreVMacGprGPRImmIntrinsic;
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def int_riscv_cv_mac_mulhhuN : ScalarCoreVMacGprGPRImmIntrinsic;
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def int_riscv_cv_mac_mulsN : ScalarCoreVMacGprGPRImmIntrinsic;
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def int_riscv_cv_mac_mulhhsN : ScalarCoreVMacGprGPRImmIntrinsic;
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def int_riscv_cv_mac_muluRN : ScalarCoreVMacGprGPRImmIntrinsic;
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def int_riscv_cv_mac_mulhhuRN : ScalarCoreVMacGprGPRImmIntrinsic;
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def int_riscv_cv_mac_mulsRN : ScalarCoreVMacGprGPRImmIntrinsic;
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def int_riscv_cv_mac_mulhhsRN : ScalarCoreVMacGprGPRImmIntrinsic;
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def int_riscv_cv_mac_macuN : ScalarCoreVMacGprGprGprImmIntrinsic;
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def int_riscv_cv_mac_machhuN : ScalarCoreVMacGprGprGprImmIntrinsic;
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def int_riscv_cv_mac_macsN : ScalarCoreVMacGprGprGprImmIntrinsic;
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def int_riscv_cv_mac_machhsN : ScalarCoreVMacGprGprGprImmIntrinsic;
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def int_riscv_cv_mac_macuRN : ScalarCoreVMacGprGprGprImmIntrinsic;
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def int_riscv_cv_mac_machhuRN : ScalarCoreVMacGprGprGprImmIntrinsic;
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def int_riscv_cv_mac_macsRN : ScalarCoreVMacGprGprGprImmIntrinsic;
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def int_riscv_cv_mac_machhsRN : ScalarCoreVMacGprGprGprImmIntrinsic;
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} // TargetPrefix = "riscv"
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