6024e5c395
clang 20.0.0 (based on r547379) from build 12806354. Bug: http://b/379133546 Test: N/A Change-Id: I2eb8938af55d809de674be63cb30cf27e801862b Upstream-Commit: ad834e67b1105d15ef907f6255d4c96e8e733f57
412 lines
14 KiB
C++
412 lines
14 KiB
C++
//===------ aarch32.h - Generic JITLink arm/thumb utilities -----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// Generic utilities for graphs representing arm/thumb objects.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_EXECUTIONENGINE_JITLINK_AARCH32
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#define LLVM_EXECUTIONENGINE_JITLINK_AARCH32
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#include "TableManager.h"
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#include "llvm/ExecutionEngine/JITLink/JITLink.h"
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#include "llvm/ExecutionEngine/Orc/Shared/ExecutorAddress.h"
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#include "llvm/Support/ARMBuildAttributes.h"
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#include "llvm/Support/Error.h"
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namespace llvm {
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namespace jitlink {
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namespace aarch32 {
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/// Check whether the given target flags are set for this Symbol.
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bool hasTargetFlags(Symbol &Sym, TargetFlagsType Flags);
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/// JITLink-internal AArch32 fixup kinds
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enum EdgeKind_aarch32 : Edge::Kind {
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///
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/// Relocations of class Data respect target endianness (unless otherwise
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/// specified)
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///
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FirstDataRelocation = Edge::FirstRelocation,
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/// Relative 32-bit value relocation
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Data_Delta32 = FirstDataRelocation,
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/// Absolute 32-bit value relocation
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Data_Pointer32,
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/// Relative 31-bit value relocation that preserves the most-significant bit
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Data_PRel31,
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/// Create GOT entry and store offset
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Data_RequestGOTAndTransformToDelta32,
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LastDataRelocation = Data_RequestGOTAndTransformToDelta32,
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///
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/// Relocations of class Arm (covers fixed-width 4-byte instruction subset)
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///
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FirstArmRelocation,
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/// Write immediate value for unconditional PC-relative branch with link.
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/// We patch the instruction opcode to account for an instruction-set state
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/// switch: we use the bl instruction to stay in ARM and the blx instruction
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/// to switch to Thumb.
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Arm_Call = FirstArmRelocation,
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/// Write immediate value for conditional PC-relative branch without link.
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/// If the branch target is not ARM, we are forced to generate an explicit
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/// interworking stub.
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Arm_Jump24,
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/// Write immediate value to the lower halfword of the destination register
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Arm_MovwAbsNC,
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/// Write immediate value to the top halfword of the destination register
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Arm_MovtAbs,
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LastArmRelocation = Arm_MovtAbs,
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///
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/// Relocations of class Thumb16 and Thumb32 (covers Thumb instruction subset)
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///
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FirstThumbRelocation,
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/// Write immediate value for unconditional PC-relative branch with link.
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/// We patch the instruction opcode to account for an instruction-set state
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/// switch: we use the bl instruction to stay in Thumb and the blx instruction
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/// to switch to ARM.
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Thumb_Call = FirstThumbRelocation,
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/// Write immediate value for PC-relative branch without link. The instruction
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/// can be made conditional by an IT block. If the branch target is not ARM,
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/// we are forced to generate an explicit interworking stub.
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Thumb_Jump24,
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/// Write immediate value to the lower halfword of the destination register
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Thumb_MovwAbsNC,
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/// Write immediate value to the top halfword of the destination register
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Thumb_MovtAbs,
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/// Write PC-relative immediate value to the lower halfword of the destination
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/// register
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Thumb_MovwPrelNC,
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/// Write PC-relative immediate value to the top halfword of the destination
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/// register
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Thumb_MovtPrel,
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LastThumbRelocation = Thumb_MovtPrel,
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/// No-op relocation
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None,
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LastRelocation = None,
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};
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/// Flags enum for AArch32-specific symbol properties
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enum TargetFlags_aarch32 : TargetFlagsType {
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ThumbSymbol = 1 << 0,
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};
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/// Human-readable name for a given CPU architecture kind
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const char *getCPUArchName(ARMBuildAttrs::CPUArch K);
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/// Get a human-readable name for the given AArch32 edge kind.
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const char *getEdgeKindName(Edge::Kind K);
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/// AArch32 uses stubs for a number of purposes, like branch range extension
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/// or interworking between Arm and Thumb instruction subsets.
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///
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/// Stub implementations vary depending on CPU architecture (v4, v6, v7),
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/// instruction subset and branch type (absolute/PC-relative).
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///
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/// For each kind of stub, the StubsFlavor defines one concrete form that is
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/// used throughout the LinkGraph.
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///
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/// Stubs are often called "veneers" in the official docs and online.
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///
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enum class StubsFlavor {
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Undefined = 0,
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pre_v7,
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v7,
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};
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/// JITLink sub-arch configuration for Arm CPU models
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struct ArmConfig {
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bool J1J2BranchEncoding = false;
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StubsFlavor Stubs = StubsFlavor::Undefined;
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// In the long term, we might want a linker switch like --target1-rel
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bool Target1Rel = false;
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};
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/// Obtain the sub-arch configuration for a given Arm CPU model.
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inline ArmConfig getArmConfigForCPUArch(ARMBuildAttrs::CPUArch CPUArch) {
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ArmConfig ArmCfg;
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if (CPUArch == ARMBuildAttrs::v7 || CPUArch >= ARMBuildAttrs::v7E_M) {
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ArmCfg.J1J2BranchEncoding = true;
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ArmCfg.Stubs = StubsFlavor::v7;
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} else {
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ArmCfg.J1J2BranchEncoding = false;
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ArmCfg.Stubs = StubsFlavor::pre_v7;
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}
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return ArmCfg;
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}
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/// Immutable pair of halfwords, Hi and Lo, with overflow check
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struct HalfWords {
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constexpr HalfWords() : Hi(0), Lo(0) {}
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constexpr HalfWords(uint32_t Hi, uint32_t Lo) : Hi(Hi), Lo(Lo) {
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assert(isUInt<16>(Hi) && "Overflow in first half-word");
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assert(isUInt<16>(Lo) && "Overflow in second half-word");
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}
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const uint16_t Hi; // First halfword
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const uint16_t Lo; // Second halfword
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};
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/// FixupInfo base class is required for dynamic lookups.
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struct FixupInfoBase {
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static const FixupInfoBase *getDynFixupInfo(Edge::Kind K);
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virtual ~FixupInfoBase() {}
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};
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/// FixupInfo checks for Arm edge kinds work on 32-bit words
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struct FixupInfoArm : public FixupInfoBase {
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bool (*checkOpcode)(uint32_t Wd) = nullptr;
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};
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/// FixupInfo check for Thumb32 edge kinds work on a pair of 16-bit halfwords
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struct FixupInfoThumb : public FixupInfoBase {
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bool (*checkOpcode)(uint16_t Hi, uint16_t Lo) = nullptr;
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};
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/// Collection of named constants per fixup kind
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///
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/// Mandatory entries:
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/// Opcode - Values of the op-code bits in the instruction, with
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/// unaffected bits nulled
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/// OpcodeMask - Mask with all bits set that encode the op-code
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///
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/// Other common entries:
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/// ImmMask - Mask with all bits set that encode the immediate value
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/// RegMask - Mask with all bits set that encode the register
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///
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/// Specializations can add further custom fields without restrictions.
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///
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template <EdgeKind_aarch32 Kind> struct FixupInfo {};
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struct FixupInfoArmBranch : public FixupInfoArm {
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static constexpr uint32_t Opcode = 0x0a000000;
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static constexpr uint32_t ImmMask = 0x00ffffff;
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};
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template <> struct FixupInfo<Arm_Jump24> : public FixupInfoArmBranch {
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static constexpr uint32_t OpcodeMask = 0x0f000000;
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};
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template <> struct FixupInfo<Arm_Call> : public FixupInfoArmBranch {
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static constexpr uint32_t OpcodeMask = 0x0e000000;
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static constexpr uint32_t CondMask = 0xe0000000; // excluding BLX bit
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static constexpr uint32_t Unconditional = 0xe0000000;
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static constexpr uint32_t BitH = 0x01000000;
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static constexpr uint32_t BitBlx = 0x10000000;
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};
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struct FixupInfoArmMov : public FixupInfoArm {
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static constexpr uint32_t OpcodeMask = 0x0ff00000;
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static constexpr uint32_t ImmMask = 0x000f0fff;
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static constexpr uint32_t RegMask = 0x0000f000;
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};
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template <> struct FixupInfo<Arm_MovtAbs> : public FixupInfoArmMov {
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static constexpr uint32_t Opcode = 0x03400000;
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};
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template <> struct FixupInfo<Arm_MovwAbsNC> : public FixupInfoArmMov {
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static constexpr uint32_t Opcode = 0x03000000;
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};
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template <> struct FixupInfo<Thumb_Jump24> : public FixupInfoThumb {
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static constexpr HalfWords Opcode{0xf000, 0x9000};
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static constexpr HalfWords OpcodeMask{0xf800, 0x9000};
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static constexpr HalfWords ImmMask{0x07ff, 0x2fff};
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};
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template <> struct FixupInfo<Thumb_Call> : public FixupInfoThumb {
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static constexpr HalfWords Opcode{0xf000, 0xc000};
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static constexpr HalfWords OpcodeMask{0xf800, 0xc000};
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static constexpr HalfWords ImmMask{0x07ff, 0x2fff};
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static constexpr uint16_t LoBitH = 0x0001;
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static constexpr uint16_t LoBitNoBlx = 0x1000;
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};
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struct FixupInfoThumbMov : public FixupInfoThumb {
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static constexpr HalfWords OpcodeMask{0xfbf0, 0x8000};
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static constexpr HalfWords ImmMask{0x040f, 0x70ff};
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static constexpr HalfWords RegMask{0x0000, 0x0f00};
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};
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template <> struct FixupInfo<Thumb_MovtAbs> : public FixupInfoThumbMov {
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static constexpr HalfWords Opcode{0xf2c0, 0x0000};
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};
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template <> struct FixupInfo<Thumb_MovtPrel> : public FixupInfoThumbMov {
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static constexpr HalfWords Opcode{0xf2c0, 0x0000};
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};
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template <> struct FixupInfo<Thumb_MovwAbsNC> : public FixupInfoThumbMov {
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static constexpr HalfWords Opcode{0xf240, 0x0000};
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};
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template <> struct FixupInfo<Thumb_MovwPrelNC> : public FixupInfoThumbMov {
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static constexpr HalfWords Opcode{0xf240, 0x0000};
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};
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/// Helper function to read the initial addend for Data-class relocations.
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Expected<int64_t> readAddendData(LinkGraph &G, Block &B, Edge::OffsetT Offset,
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Edge::Kind Kind);
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/// Helper function to read the initial addend for Arm-class relocations.
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Expected<int64_t> readAddendArm(LinkGraph &G, Block &B, Edge::OffsetT Offset,
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Edge::Kind Kind);
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/// Helper function to read the initial addend for Thumb-class relocations.
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Expected<int64_t> readAddendThumb(LinkGraph &G, Block &B, Edge::OffsetT Offset,
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Edge::Kind Kind, const ArmConfig &ArmCfg);
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/// Read the initial addend for a REL-type relocation. It's the value encoded
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/// in the immediate field of the fixup location by the compiler.
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inline Expected<int64_t> readAddend(LinkGraph &G, Block &B,
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Edge::OffsetT Offset, Edge::Kind Kind,
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const ArmConfig &ArmCfg) {
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if (Kind <= LastDataRelocation)
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return readAddendData(G, B, Offset, Kind);
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if (Kind <= LastArmRelocation)
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return readAddendArm(G, B, Offset, Kind);
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if (Kind <= LastThumbRelocation)
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return readAddendThumb(G, B, Offset, Kind, ArmCfg);
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assert(Kind == None && "Not associated with a relocation class");
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return 0;
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}
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/// Helper function to apply the fixup for Data-class relocations.
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Error applyFixupData(LinkGraph &G, Block &B, const Edge &E);
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/// Helper function to apply the fixup for Arm-class relocations.
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Error applyFixupArm(LinkGraph &G, Block &B, const Edge &E);
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/// Helper function to apply the fixup for Thumb-class relocations.
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Error applyFixupThumb(LinkGraph &G, Block &B, const Edge &E,
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const ArmConfig &ArmCfg);
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/// Apply fixup expression for edge to block content.
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inline Error applyFixup(LinkGraph &G, Block &B, const Edge &E,
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const ArmConfig &ArmCfg) {
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Edge::Kind Kind = E.getKind();
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if (Kind <= LastDataRelocation)
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return applyFixupData(G, B, E);
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if (Kind <= LastArmRelocation)
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return applyFixupArm(G, B, E);
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if (Kind <= LastThumbRelocation)
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return applyFixupThumb(G, B, E, ArmCfg);
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assert(Kind == None && "Not associated with a relocation class");
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return Error::success();
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}
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/// Populate a Global Offset Table from edges that request it.
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class GOTBuilder : public TableManager<GOTBuilder> {
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public:
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static StringRef getSectionName() { return "$__GOT"; }
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bool visitEdge(LinkGraph &G, Block *B, Edge &E);
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Symbol &createEntry(LinkGraph &G, Symbol &Target);
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private:
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Section *GOTSection = nullptr;
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};
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/// Stubs builder emits non-position-independent Arm stubs for pre-v7 CPUs.
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/// These architectures have no MovT/MovW instructions and don't support Thumb2.
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/// BL is the only Thumb instruction that can generate stubs and they can always
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/// be transformed into BLX.
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class StubsManager_prev7 {
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public:
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StubsManager_prev7() = default;
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/// Name of the object file section that will contain all our stubs.
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static StringRef getSectionName() {
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return "__llvm_jitlink_aarch32_STUBS_prev7";
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}
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/// Implements link-graph traversal via visitExistingEdges()
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bool visitEdge(LinkGraph &G, Block *B, Edge &E);
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private:
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// Each stub uses a single block that can have 2 entryponts, one for Arm and
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// one for Thumb
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struct StubMapEntry {
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Block *B = nullptr;
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Symbol *ArmEntry = nullptr;
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Symbol *ThumbEntry = nullptr;
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};
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std::pair<StubMapEntry *, bool> getStubMapSlot(StringRef Name) {
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auto &&[Stubs, NewStub] = StubMap.try_emplace(Name);
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return std::make_pair(&Stubs->second, NewStub);
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}
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Symbol *getOrCreateSlotEntrypoint(LinkGraph &G, StubMapEntry &Slot,
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bool Thumb);
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DenseMap<StringRef, StubMapEntry> StubMap;
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Section *StubsSection = nullptr;
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};
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/// Stubs builder for v7 emits non-position-independent Arm and Thumb stubs.
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class StubsManager_v7 {
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public:
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StubsManager_v7() = default;
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/// Name of the object file section that will contain all our stubs.
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static StringRef getSectionName() {
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return "__llvm_jitlink_aarch32_STUBS_v7";
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}
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/// Implements link-graph traversal via visitExistingEdges().
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bool visitEdge(LinkGraph &G, Block *B, Edge &E);
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private:
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// Two slots per external: Arm and Thumb
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using StubMapEntry = std::tuple<Symbol *, Symbol *>;
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Symbol *&getStubSymbolSlot(StringRef Name, bool Thumb) {
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StubMapEntry &Stubs = StubMap.try_emplace(Name).first->second;
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if (Thumb)
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return std::get<1>(Stubs);
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return std::get<0>(Stubs);
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}
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DenseMap<StringRef, StubMapEntry> StubMap;
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Section *StubsSection = nullptr;
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};
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} // namespace aarch32
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} // namespace jitlink
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} // namespace llvm
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#endif // LLVM_EXECUTIONENGINE_JITLINK_AARCH32
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