6024e5c395
clang 20.0.0 (based on r547379) from build 12806354. Bug: http://b/379133546 Test: N/A Change-Id: I2eb8938af55d809de674be63cb30cf27e801862b Upstream-Commit: ad834e67b1105d15ef907f6255d4c96e8e733f57
120 lines
4.2 KiB
C++
120 lines
4.2 KiB
C++
//===- DetectDeadLanes.h - SubRegister Lane Usage Analysis --*- C++ -*-----===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// Analysis that tracks defined/used subregister lanes across COPY instructions
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/// and instructions that get lowered to a COPY (PHI, REG_SEQUENCE,
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/// INSERT_SUBREG, EXTRACT_SUBREG).
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/// The information is used to detect dead definitions and the usage of
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/// (completely) undefined values and mark the operands as such.
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/// This pass is necessary because the dead/undef status is not obvious anymore
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/// when subregisters are involved.
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///
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/// Example:
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/// %0 = some definition
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/// %1 = IMPLICIT_DEF
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/// %2 = REG_SEQUENCE %0, sub0, %1, sub1
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/// %3 = EXTRACT_SUBREG %2, sub1
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/// = use %3
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/// The %0 definition is dead and %3 contains an undefined value.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_DETECTDEADLANES_H
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#define LLVM_CODEGEN_DETECTDEADLANES_H
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#include "llvm/ADT/BitVector.h"
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#include "llvm/MC/LaneBitmask.h"
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#include <deque>
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namespace llvm {
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class MachineInstr;
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class MachineOperand;
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class MachineRegisterInfo;
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class TargetRegisterInfo;
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class DeadLaneDetector {
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public:
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/// Contains a bitmask of which lanes of a given virtual register are
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/// defined and which ones are actually used.
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struct VRegInfo {
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LaneBitmask UsedLanes;
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LaneBitmask DefinedLanes;
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};
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DeadLaneDetector(const MachineRegisterInfo *MRI,
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const TargetRegisterInfo *TRI);
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/// Update the \p DefinedLanes and the \p UsedLanes for all virtual registers.
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void computeSubRegisterLaneBitInfo();
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const VRegInfo &getVRegInfo(unsigned RegIdx) const {
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return VRegInfos[RegIdx];
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}
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bool isDefinedByCopy(unsigned RegIdx) const {
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return DefinedByCopy.test(RegIdx);
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}
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private:
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/// Add used lane bits on the register used by operand \p MO. This translates
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/// the bitmask based on the operands subregister, and puts the register into
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/// the worklist if any new bits were added.
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void addUsedLanesOnOperand(const MachineOperand &MO, LaneBitmask UsedLanes);
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/// Given a bitmask \p UsedLanes for the used lanes on a def output of a
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/// COPY-like instruction determine the lanes used on the use operands
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/// and call addUsedLanesOnOperand() for them.
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void transferUsedLanesStep(const MachineInstr &MI, LaneBitmask UsedLanes);
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/// Given a use regiser operand \p Use and a mask of defined lanes, check
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/// if the operand belongs to a lowersToCopies() instruction, transfer the
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/// mask to the def and put the instruction into the worklist.
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void transferDefinedLanesStep(const MachineOperand &Use,
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LaneBitmask DefinedLanes);
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public:
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/// Given a mask \p DefinedLanes of lanes defined at operand \p OpNum
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/// of COPY-like instruction, determine which lanes are defined at the output
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/// operand \p Def.
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LaneBitmask transferDefinedLanes(const MachineOperand &Def, unsigned OpNum,
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LaneBitmask DefinedLanes) const;
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/// Given a mask \p UsedLanes used from the output of instruction \p MI
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/// determine which lanes are used from operand \p MO of this instruction.
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LaneBitmask transferUsedLanes(const MachineInstr &MI, LaneBitmask UsedLanes,
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const MachineOperand &MO) const;
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private:
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LaneBitmask determineInitialDefinedLanes(unsigned Reg);
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LaneBitmask determineInitialUsedLanes(unsigned Reg);
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const MachineRegisterInfo *MRI;
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const TargetRegisterInfo *TRI;
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void PutInWorklist(unsigned RegIdx) {
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if (WorklistMembers.test(RegIdx))
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return;
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WorklistMembers.set(RegIdx);
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Worklist.push_back(RegIdx);
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}
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std::unique_ptr<VRegInfo[]> VRegInfos;
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/// Worklist containing virtreg indexes.
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std::deque<unsigned> Worklist;
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BitVector WorklistMembers;
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/// This bitvector is set for each vreg index where the vreg is defined
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/// by an instruction where lowersToCopies()==true.
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BitVector DefinedByCopy;
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};
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} // end namespace llvm
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#endif // LLVM_CODEGEN_DETECTDEADLANES_H
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