261 lines
6.7 KiB
C
261 lines
6.7 KiB
C
#ifndef ___SUKISU_KPM_H
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#define ___SUKISU_KPM_H
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int sukisu_handle_kpm(unsigned long arg3, unsigned long arg4, unsigned long arg5);
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int sukisu_is_kpm_control_code(unsigned long arg2);
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// KPM控制代码
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#define CMD_KPM_CONTROL 28
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#define CMD_KPM_CONTROL_MAX 34
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// 控制代码
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// prctl(xxx, xxx, 1, "PATH", "ARGS")
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// success return 0, error return -N
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#define SUKISU_KPM_LOAD 28
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// prctl(xxx, xxx, 2, "NAME")
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// success return 0, error return -N
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#define SUKISU_KPM_UNLOAD 29
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// num = prctl(xxx, xxx, 3)
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// error return -N
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// success return +num or 0
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#define SUKISU_KPM_NUM 30
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// prctl(xxx, xxx, 4, Buffer, BufferSize)
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// success return +out, error return -N
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#define SUKISU_KPM_LIST 31
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// prctl(xxx, xxx, 5, "NAME", Buffer[256])
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// success return +out, error return -N
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#define SUKISU_KPM_INFO 32
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// prctl(xxx, xxx, 6, "NAME", "ARGS")
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// success return KPM's result value
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// error return -N
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#define SUKISU_KPM_CONTROL 33
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// prctl(xxx, xxx, 7)
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// success will printf to stdout and return 0
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// error will return -1
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#define SUKISU_KPM_PRINT 34
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/* A64 instructions are always 32 bits. */
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#define AARCH64_INSN_SIZE 4
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/*
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* ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a
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* Section C3.1 "A64 instruction index by encoding":
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* AArch64 main encoding table
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* Bit position
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* 28 27 26 25 Encoding Group
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* 0 0 - - Unallocated
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* 1 0 0 - Data processing, immediate
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* 1 0 1 - Branch, exception generation and system instructions
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* - 1 - 0 Loads and stores
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* - 1 0 1 Data processing - register
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* 0 1 1 1 Data processing - SIMD and floating point
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* 1 1 1 1 Data processing - SIMD and floating point
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* "-" means "don't care"
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*/
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enum aarch64_insn_encoding_class
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{
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AARCH64_INSN_CLS_UNKNOWN, /* UNALLOCATED */
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AARCH64_INSN_CLS_DP_IMM, /* Data processing - immediate */
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AARCH64_INSN_CLS_DP_REG, /* Data processing - register */
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AARCH64_INSN_CLS_DP_FPSIMD, /* Data processing - SIMD and FP */
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AARCH64_INSN_CLS_LDST, /* Loads and stores */
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AARCH64_INSN_CLS_BR_SYS, /* Branch, exception generation and
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* system instructions */
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};
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enum aarch64_insn_hint_op
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{
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AARCH64_INSN_HINT_NOP = 0x0 << 5,
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AARCH64_INSN_HINT_YIELD = 0x1 << 5,
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AARCH64_INSN_HINT_WFE = 0x2 << 5,
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AARCH64_INSN_HINT_WFI = 0x3 << 5,
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AARCH64_INSN_HINT_SEV = 0x4 << 5,
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AARCH64_INSN_HINT_SEVL = 0x5 << 5,
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};
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enum aarch64_insn_imm_type
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{
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AARCH64_INSN_IMM_ADR,
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AARCH64_INSN_IMM_26,
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AARCH64_INSN_IMM_19,
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AARCH64_INSN_IMM_16,
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AARCH64_INSN_IMM_14,
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AARCH64_INSN_IMM_12,
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AARCH64_INSN_IMM_9,
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AARCH64_INSN_IMM_7,
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AARCH64_INSN_IMM_6,
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AARCH64_INSN_IMM_S,
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AARCH64_INSN_IMM_R,
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AARCH64_INSN_IMM_MAX
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};
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enum aarch64_insn_register_type
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{
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AARCH64_INSN_REGTYPE_RT,
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AARCH64_INSN_REGTYPE_RN,
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AARCH64_INSN_REGTYPE_RT2,
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AARCH64_INSN_REGTYPE_RM,
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AARCH64_INSN_REGTYPE_RD,
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AARCH64_INSN_REGTYPE_RA,
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};
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enum aarch64_insn_register
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{
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AARCH64_INSN_REG_0 = 0,
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AARCH64_INSN_REG_1 = 1,
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AARCH64_INSN_REG_2 = 2,
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AARCH64_INSN_REG_3 = 3,
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AARCH64_INSN_REG_4 = 4,
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AARCH64_INSN_REG_5 = 5,
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AARCH64_INSN_REG_6 = 6,
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AARCH64_INSN_REG_7 = 7,
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AARCH64_INSN_REG_8 = 8,
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AARCH64_INSN_REG_9 = 9,
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AARCH64_INSN_REG_10 = 10,
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AARCH64_INSN_REG_11 = 11,
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AARCH64_INSN_REG_12 = 12,
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AARCH64_INSN_REG_13 = 13,
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AARCH64_INSN_REG_14 = 14,
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AARCH64_INSN_REG_15 = 15,
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AARCH64_INSN_REG_16 = 16,
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AARCH64_INSN_REG_17 = 17,
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AARCH64_INSN_REG_18 = 18,
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AARCH64_INSN_REG_19 = 19,
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AARCH64_INSN_REG_20 = 20,
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AARCH64_INSN_REG_21 = 21,
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AARCH64_INSN_REG_22 = 22,
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AARCH64_INSN_REG_23 = 23,
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AARCH64_INSN_REG_24 = 24,
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AARCH64_INSN_REG_25 = 25,
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AARCH64_INSN_REG_26 = 26,
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AARCH64_INSN_REG_27 = 27,
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AARCH64_INSN_REG_28 = 28,
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AARCH64_INSN_REG_29 = 29,
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AARCH64_INSN_REG_FP = 29, /* Frame pointer */
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AARCH64_INSN_REG_30 = 30,
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AARCH64_INSN_REG_LR = 30, /* Link register */
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AARCH64_INSN_REG_ZR = 31, /* Zero: as source register */
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AARCH64_INSN_REG_SP = 31 /* Stack pointer: as load/store base reg */
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};
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enum aarch64_insn_variant
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{
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AARCH64_INSN_VARIANT_32BIT,
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AARCH64_INSN_VARIANT_64BIT
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};
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enum aarch64_insn_condition
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{
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AARCH64_INSN_COND_EQ = 0x0, /* == */
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AARCH64_INSN_COND_NE = 0x1, /* != */
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AARCH64_INSN_COND_CS = 0x2, /* unsigned >= */
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AARCH64_INSN_COND_CC = 0x3, /* unsigned < */
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AARCH64_INSN_COND_MI = 0x4, /* < 0 */
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AARCH64_INSN_COND_PL = 0x5, /* >= 0 */
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AARCH64_INSN_COND_VS = 0x6, /* overflow */
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AARCH64_INSN_COND_VC = 0x7, /* no overflow */
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AARCH64_INSN_COND_HI = 0x8, /* unsigned > */
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AARCH64_INSN_COND_LS = 0x9, /* unsigned <= */
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AARCH64_INSN_COND_GE = 0xa, /* signed >= */
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AARCH64_INSN_COND_LT = 0xb, /* signed < */
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AARCH64_INSN_COND_GT = 0xc, /* signed > */
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AARCH64_INSN_COND_LE = 0xd, /* signed <= */
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AARCH64_INSN_COND_AL = 0xe, /* always */
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};
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enum aarch64_insn_branch_type
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{
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AARCH64_INSN_BRANCH_NOLINK,
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AARCH64_INSN_BRANCH_LINK,
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AARCH64_INSN_BRANCH_RETURN,
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AARCH64_INSN_BRANCH_COMP_ZERO,
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AARCH64_INSN_BRANCH_COMP_NONZERO,
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};
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enum aarch64_insn_size_type
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{
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AARCH64_INSN_SIZE_8,
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AARCH64_INSN_SIZE_16,
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AARCH64_INSN_SIZE_32,
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AARCH64_INSN_SIZE_64,
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};
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enum aarch64_insn_ldst_type
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{
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AARCH64_INSN_LDST_LOAD_REG_OFFSET,
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AARCH64_INSN_LDST_STORE_REG_OFFSET,
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AARCH64_INSN_LDST_LOAD_PAIR_PRE_INDEX,
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AARCH64_INSN_LDST_STORE_PAIR_PRE_INDEX,
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AARCH64_INSN_LDST_LOAD_PAIR_POST_INDEX,
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AARCH64_INSN_LDST_STORE_PAIR_POST_INDEX,
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};
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enum aarch64_insn_adsb_type
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{
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AARCH64_INSN_ADSB_ADD,
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AARCH64_INSN_ADSB_SUB,
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AARCH64_INSN_ADSB_ADD_SETFLAGS,
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AARCH64_INSN_ADSB_SUB_SETFLAGS
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};
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enum aarch64_insn_movewide_type
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{
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AARCH64_INSN_MOVEWIDE_ZERO,
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AARCH64_INSN_MOVEWIDE_KEEP,
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AARCH64_INSN_MOVEWIDE_INVERSE
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};
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enum aarch64_insn_bitfield_type
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{
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AARCH64_INSN_BITFIELD_MOVE,
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AARCH64_INSN_BITFIELD_MOVE_UNSIGNED,
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AARCH64_INSN_BITFIELD_MOVE_SIGNED
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};
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enum aarch64_insn_data1_type
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{
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AARCH64_INSN_DATA1_REVERSE_16,
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AARCH64_INSN_DATA1_REVERSE_32,
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AARCH64_INSN_DATA1_REVERSE_64,
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};
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enum aarch64_insn_data2_type
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{
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AARCH64_INSN_DATA2_UDIV,
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AARCH64_INSN_DATA2_SDIV,
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AARCH64_INSN_DATA2_LSLV,
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AARCH64_INSN_DATA2_LSRV,
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AARCH64_INSN_DATA2_ASRV,
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AARCH64_INSN_DATA2_RORV,
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};
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enum aarch64_insn_data3_type
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{
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AARCH64_INSN_DATA3_MADD,
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AARCH64_INSN_DATA3_MSUB,
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};
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enum aarch64_insn_logic_type
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{
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AARCH64_INSN_LOGIC_AND,
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AARCH64_INSN_LOGIC_BIC,
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AARCH64_INSN_LOGIC_ORR,
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AARCH64_INSN_LOGIC_ORN,
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AARCH64_INSN_LOGIC_EOR,
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AARCH64_INSN_LOGIC_EON,
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AARCH64_INSN_LOGIC_AND_SETFLAGS,
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AARCH64_INSN_LOGIC_BIC_SETFLAGS
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};
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#define AARCH64_INSN_IMM_MOVNZ AARCH64_INSN_IMM_MAX
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#define AARCH64_INSN_IMM_MOVK AARCH64_INSN_IMM_16
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#endif |